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Test and testability techniques for open defects in RAM addressdecoders

机译:RAM地址中开放缺陷的测试和可测试性技术解码器

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It is a prevalent assumption that all RAM address decoder defectscan be modelled as RAM array faults influencing one or more RAM cells.Therefore, can be implicitly detected by testing the RAM matrix with themarch tests. Recently, we came across some failures in embedded SRAMswhich were not detected by the march tests. The carried out analysisdemonstrated the presence of open defects in address decoders thatcannot be modelled as the conventional coupling faults, therefore, arenot detected by the march tests. In this article, we present the testand testability strategies for such hard-to-detect open defects
机译:一个普遍的假设是所有RAM地址解码器都有缺陷 可以建模为影响一个或多个RAM单元的RAM阵列故障。 因此,可以通过测试RAM矩阵来隐式检测 行军测试。最近,我们遇到了嵌入式SRAM中的一些故障 行军测试未检测到。进行分析 证明了地址解码器中存在开放缺陷, 不能像传统的耦合故障那样建模,因此, 行军测试未检测到。在本文中,我们介绍了测试 此类难以发现的开放缺陷的测试方法和可测试性策略

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