IC technologies are approaching the ultimate limits of silicon interms of channel width, power supply and speed. By approaching theselimits, circuits are becoming increasingly sensitive to noise, whichwill result in unacceptable rates of soft-errors. Manufacturing testingand periodic testing cannot cope with soft errors. Thus, fault toleranttechniques will become necessary even for commodity applications. Thiswork considers the implementation of a new soft error tolerancetechnique based on time redundancy. Arithmetic circuits were used astest vehicle to validate the approach. Simulations and performanceevaluation of the proposed fault-tolerance technique were made usingin-house tools realized around an event driven simulator. The obtainedresults show that tolerance of soft errors can be achieved at low cost
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