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A Formal Model of Lower System Layers

机译:下层系统层的正式模型

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摘要

We present a formal model of the bit transmission between registers with arbitrary clock periods. Our model considers precise timing parameters, as well as metastability. We formally define the behavior of registers over time. From that definition, we prove, under certain conditions, that data are properly transmitted. We discuss how to incorporate the model in a purely digital model. The hypotheses of our main theorem define conditions that must be satisfied by the purely digital part of the system to preserve correctness
机译:我们提出了具有任意时钟周期的寄存器之间的位传输的形式化模型。我们的模型考虑了精确的时序参数以及亚稳性。我们正式定义了随时间变化的寄存器行为。根据该定义,我们证明在某些条件下可以正确传输数据。我们讨论了如何将模型合并到纯数字模型中。我们的主要定理的假设定义了系统的纯数字部分必须满足的条件,以保持正确性

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