Impact of reconfiguration logic on the optimization ofdefect-tolerant integrated circuits

摘要

Two aspects of the impact of reconfiguration logic on theoptimization of defect-tolerant integrated circuits (ICs) are analyzed.An important consequence to design decisions of neglectingreconfiguration logic is presented. Expressions are developed to predictthe number of transistors necessary to implement the reconfigurationlogic of a simple defect-tolerance strategy using CMOS technology. Theresults show that neglecting this reconfiguration logic can lead toinappropriate design decisions. An example of a fine-grain logic arrayis presented to demonstrate the latter conclusion