The author presents basic electrical models to calculateequivalent inductances (noises) for a 179 pin grid array package as afunction of ground/power/signals pin organizations. A full experimentalinductances measurement based on time domain reflectometry and frequencymethod is also presented. A specific test vehicle was elaborated toavoid fixturing noise. Calculated and measured signal effectiveinductance values are compared. Each integrated circuit logic family hasa specific switching point. Thus, adequate ground/power/signalorganization depends on the technology used. For some logic familieslike TTL (transistor transistor logic) and DCFL in silicon and GaAstechnologies, the switching point near the ground voltage indicates thatthe critical path is ground. On other hand, the internal switchingcurrent becomes comparable to the input buffers (30-50 mAs). Thus, theground/signal/power organization of output buffers must take intoaccount the internal logic I/O's (input/outputs). The noises are asfunction of the number of IO buffers and internal logic IO gates
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