Numerical and experimental investigations of large IC flip chipattach

摘要

Because flip chips can achieve high electrical interconnect speed,high density, and low profiles, a team from the Fraunhofer Institute forReliability and Microintegration in Berlin and from Georgia Techundertake a study examining the extreme limits of flip chip input/output(I/O) capabilities and physical dimensions. Their starting point is aSIA estimate of memory requirements, based on Moore's Law, for the year2012. In order to study the limitations of flip chip technology thegroups are working on both, advanced thermomechanical simulation andhands-on interconnection technology resulting in the design of four flipchips. They have the dimensions of 10×10 mm²,20×20 mm², 30×30 mm², and 40×40mm². With these designs both, the simulation and theinterconnection technology departments of Fraunhofer IZM start toevaluate the feasibility of flip chips beyond 20×20 mm²