Stagger Tuning for BW extension in Transimpedance Amplifiers

摘要

This article explains Stagger tuning of two stage TIA. The method reduces effect of capacitances of the transistor. The process of stagger tuning has been shown using zero-pole analysis. The feasibility of the method is confirmed using CMOS technology (i.e. 90nm). 3-dB bandwidths of 40GHz when using 50fF PD capacitance and 5fF load with consumption of 4.4mW can be achieved.