Area Optimization of CMOS Full Adder Design Using 3T XOR

摘要

GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of area and power consumption of digital circuits. In this design XOR gate is designed using 3 transistors and CMOS full adder is designed based on two 3T XOR and one 2T Mux. Using 8 transistors the full adder is designed in this paper and voltage scaling also done by reducing supply voltage. In this proposed full adder, the power consumption 4.604µW is achieved and the total area is 144µm².