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GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling

机译:具有自适应电压和频率缩放功能的系统的GPU加速时间仿真

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Timing validation of systems with adaptive voltage-and frequency scaling (AVFS) requires an accurate timing model under multiple operating points. Simulating such a model at gate level is extremely time-consuming, and the state-of-the-art compromises both accuracy and compute efficiency.This paper presents a method for dynamic gate delay modeling on graphics processing unit (GPU) accelerators which is based on polynomial approximation with offline statistical learning using regression analysis. It provides glitch-accurate switching activity information for gates and designs under varying supply voltages with negligible memory and performance impact. Parallelism from the evaluation of operating conditions, gates and stimuli is exploited simultaneously to utilize the high arithmetic computing throughput of GPUs. This way, large-scale design space exploration of AVFS-based systems is enabled. Experimental results demonstrate the efficiency and accuracy of the presented approach showing speedups of three orders of magnitude over conventional time simulation that supports static delays only.
机译:具有自适应电压和频率缩放(AVFS)的系统的时序验证需要在多个工作点下建立准确的时序模型。在门级模拟这样的模型非常耗时,而现有技术却在准确性和计算效率上都有所折衷。本文提出了一种基于图形处理器(GPU)加速器的动态门延迟建模方法。使用回归分析的离线统计学习进行多项式逼近。它在变化的电源电压下为门和设计提供了故障准确的开关活动信息,而对存储器和性能的影响则微不足道。同时评估工作条件,门和刺激的并行性,以利用GPU的高算术计算吞吐量。这样,就可以对基于AVFS的系统进行大规模的设计空间探索。实验结果证明了所提出方法的效率和准确性,与仅支持静态延迟的常规时间仿真相比,该方法显示出三个数量级的加速。

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