98 Endurance Error Reduction by Hard_Verify for 40nm TaOx based ReRAM

摘要

This paper proposes Hard_Verify technique for 40nm TaO $_{X} -$based resistive random access memories (ReRAM). The proposed technique is a new Verify operation leads to enhancing the reliability of endurance. Verify criteria of proposed Hard_Verify is changed to expand executing area as compared with conventional Verify. With Hard_Verify, measured Bit-Error Rate (BER) of low resistance state (LRS) is reduced by 98% at high endurance cycles $= 10 ^{5, }$as compared with conventional Verify. In addition, the optimal write process applying Hard_Verify is investigated to reduce tail error cells (tail bits) at high endurance cycles. To explain such enhancement of the endurance reliability, the physical model is discussed based on oxygen vacancy $(mathrm{V}_{O})$ diffusion.