The paper proposes a new VLSI architecture for morphological filters and presents its design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architectures by using a feedback loop path to reuse partial results and a decoder/encoder pair comparator to detect minimum/maximum values. In addition, the proposed architecture requires one common architecture for both dilation and erosion and a fewer number of operations. Moreover, it can be easily extended for larger size morphological operations. We developed VHDL models, performed logic synthesis using the SYNOPSYS/sup TM/ CAD tool. We used the 0.8 /spl mu/m SOG cell library and performed function and timing simulations. The proposed morphological filter chip has been fabricated. The total number of gates is only 2667 and the clock frequency is 30 MHz-that meets real time image processing requirements of the standard of ITU-R BT.601 image format.
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机译：本文提出了一种用于形态过滤器的新VLSI架构，并提供了其设计和实现。通过使用反馈环路路径将拟议的架构与现有架构相比，所提出的架构可以显着降低硬件成本，以重用部分结果和解码器/编码器对比较器以检测最小/最大值。此外，所提出的架构需要一个常见的架构，用于扩张和侵蚀和较少的操作。此外，它可以很容易地延长较大尺寸的形态操作。我们开发了VHDL模型，使用Synopsys / Sup TM / CAD工具进行了逻辑合成。我们使用了0.8 / SPL MU / M SOG单元库并执行了函数和定时仿真。已经制造了所提出的形态过滤芯片。门的总数仅为2667，时钟频率为30 MHz - 符合ITU-R BT.601标准的实时图像处理要求。
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