A morphological filter chip using a modified decoding function

摘要

This paper proposes a new very large scale integrationnarchitecture for cost-effective morphological filters and presents itsndesign and chip implementation. The proposed architecture can reduce thenhardware cost by using a feedback loop path and a decoder/encoder pairncomparator. The feedback loop path can reuse partial results to reducenthe number of add/subtract units. The decoder/encoder pair comparatornusing a modified decoding function can reduce the gate count andnpropagation delay especially when the size of morphological operationsnincreases. We used the 0.8-Μm SOG cell library (KG60 K) and the totalnnumber of gates is only 2667. The proposed morphological filter chip hasnactually been fabricated and is running at 30 MHz that meets thenreal-time image processing requirement of the ITU-R BT.601nstandard