The paper proposes a new VLSI architecture for morphological filters and presents its design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architectures by using a feedback loop path to reuse partial results and a decoder/encoder pair comparator to detect minimum/maximum values. In addition, the proposed architecture requires one common architecture for both dilation and erosion and a fewer number of operations. Moreover, it can be easily extended for larger size morphological operations. We developed VHDL models, performed logic synthesis using the SYNOPSYS/sup TM/ CAD tool. We used the 0.8 /spl mu/m SOG cell library and performed function and timing simulations. The proposed morphological filter chip has been fabricated. The total number of gates is only 2667 and the clock frequency is 30 MHz-that meets real time image processing requirements of the standard of ITU-R BT.601 image format.
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机译：本文提出了一种用于形态学滤波器的新型VLSI架构，并提出了其设计和实现。与现有体系结构相比，通过使用反馈环路路径重用部分结果以及使用解码器/编码器对比较器来检测最小值/最大值，与现有体系结构相比，该体系结构可以显着降低硬件成本。另外，所提出的架构需要一种用于扩张和腐蚀的通用架构，并且需要较少的操作。而且，它可以很容易地扩展到更大尺寸的形态学操作。我们开发了VHDL模型，并使用SYNOPSYS / sup TM / CAD工具进行了逻辑综合。我们使用0.8 / spl mu / m SOG单元库并执行功能和时序仿真。所提出的形态滤波器芯片已被制造。门的总数仅为2667，时钟频率为30 MHz，符合ITU-R BT.601图像格式标准的实时图像处理要求。
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