Sensitivity Analysis of Local Soldermask and Coverlay in High Speed Transimission Lines for DDR5 Applications to Reduce FEXT

摘要

This article investigated the effects of local solder-mask and overlay structure changes on crosstalk. This structure is based on a four-layer high-speed PCB on a computer DDR5 board. Our goal is to use the obtained simulation results to locate the optimal response that not only meets the performance requirements but is also robust to geometric changes caused by manufacturing tolerances. These two methods have a good correlation with the simulation results and show strong capabilities in the practical applications.