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W-Band Divide-by-3 Injection-Locked Frequency Divider Using Stacked Cross-Coupled Transistors in 90 nm CMOS

机译:使用堆叠交叉耦合晶体管在90 nm CMOS中的W波段三分频注入锁定分频器

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We demonstrate two low-power and wide-locking-range W-band CMOS divide-by-3 injection-locked frequency dividers (ILFD3) using stacked cross-coupled-transistor (CCT) topology. The first ILFD3 (ILFD31) uses an on-chip balun to transform the single input signal to differential output signals, which are amplified by the lower CCTs and then inject the source terminals of the upper CCTs. The second ILFD3 (ILFD32) uses a tail transistor to amplify the injection signal, which then injects the source terminals of the lower CCTs. Due to the strong second harmonic signal (2finj) at the source terminals of the upper CCTs, there are notable locked fundamental signals (finj) at the drain terminals of the upper CCTs. ILFD31 consumes a low power of 1.6 mW, and achieves a locking range of 3.4 GHz (92.5-95.9 GHz). ILFD32 consumes a low power of 0.13 mW, and achieves an excellent locking range of 18 GHz (91.8-109.8 GHz), one of the best results ever reported for W-band CMOS ILFD3s.
机译:我们演示了使用堆叠交叉耦合晶体管(CCT)拓扑结构的两个低功耗和宽锁定范围W波段CMOS除以3的注入锁定分频器(ILFD3)。第一个ILFD3(ILFD3 1 )使用片上巴伦将单输入信号转换为差分输出信号,这些信号由较低的CCT放大,然后注入较高的CCT的源极端子。第二个ILFD3(ILFD3 2 )使用尾部晶体管放大注入信号,然后注入较低CCT的源极端子。由于强大的二次谐波信号(2f inj )在上部CCT的源极端子上,有明显的锁定基本信号(f inj )在上部CCT的漏极端子上。 ILFD31消耗1.6 mW的低功率,并实现3.4 GHz(92.5-95.9 GHz)的锁定范围。 ILFD3 2 功耗仅为0.13 mW,并实现了18 GHz(91.8-109.8 GHz)的出色锁定范围,这是W波段CMOS ILFD3的最佳结果之一。

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