Modelling Degradation of Matched-Circuits in Operational Conditions: Active and Stand-by Modes

摘要

In today's technology [1], degradation in IC standby mode cannot be neglected, especially for high power consumption devices whose standby mode have seen a high junction temperature and DC voltage stress. In this study, degradation of a matched-circuit Peripheral Component Interconnect express (PCIe) in active and standby modes will be discussed. A model is proposed and confirmed with experimental data. While work is done on a typical circuit PCI-express; its framework can be used for other similar designs such as Serial Advanced Technology Attachment (SATA) ports, Transition Minimized-Differential-Signaling (TMDS), Serializer/Deserializer (SerDes), etc.