Allowing Switching off Periphery Voltage Island Instead of Doing it per Instance Through Periphery VDD Collapse in SRAMs

摘要

In typical SoC Designs, having multiple SRAM cores on single chip has demanded switching off idle cores to attain lowest possible power down leakage because of SRAMs. This paper introduces a novel method called Periphery VDD Collapse to address this aspect by achieving nearly zero periphery leakage when in power down mode. By virtue of having switches outside memory, this feature allows designers to switch off supply for a voltage island containing multiple cores instead of doing it per memory. A novel level shifter interface is implemented to characteristically isolate periphery from bit cell array and allow periphery to be switched off while retaining data present in bit cell array. Experimental results show very minimal change in power and leakage compared to the case when power gates are embedded inside, but saves up to 10% area after being moved outside on chip.