Power Supply Noise Coupling Mitigation across High Speed Serial Links

摘要

In the SoC (System on Chip) environment, one I/O will have power supply noise coupling from other I/Os due to the proximity of different I/O's noise source and lack of mitigation mechanisms at the victim. It becomes more important if the victim I/O is very sensitive to certain noise spectrum. This paper describes a methodical approach for characterizing the Power delivery network coupling from one I/O to the other I/O & also provides solution to reduce this coupling noise which is validated across different Silicon. Early identification of such coupling mechanisms is very important, as the necessary mechanisms to mitigate the coupling can be implemented in the SoC development phase.