CLOCK PSIJ Study under different PDN choices in LPDDR3 systems

摘要

In this paper, power supply induced jitter on clock lane is investigated under different Power Delivery Network configurations for a Low Power Double Data Rate system. Novelty of this paper is in the identification of best topology for sharing of power supplies between clock lane, command-address bus, and data bus at the system level consisting of input-output buffers ring, package and board.