Optimizing the Efficiency of Data Transfer in Dataflow Architectures

摘要

Dataflow architectures have been proposed in response to several emerging problems in processor design, such as computational efficiency, design complexity and power efficiency. A dataflow architecture is composed of multiple processing elements (PEs) that are organized into the form of grid. The instructions are compiled by compiler and are explicitly mapped to the PE grid using the instruction placement algorithm. The instruction placement algorithms generally take load balancing, low communication delay, and resource contention as input conditions, but most of them ignore the router congestion of the dataflow network. By applying three kinds of typical instruction placement algorithms on the dataflow model, we found that the dynamic packets that are transferred through the dataflow network is not evenly distributed. Due to the reason that dataflow network usually adopts the uniform structure for each router, congestion is susceptible to occur in the directions dealing with larger load. Partial congestion of the network will degrade the transfer efficiency of the dataflow network, which directly affects the execution efficiency of the dataflow processor. In order to optimize the transfer efficiency of routers and execution efficiency of dataflow processor under unevenly distributed network load, we proposed a cost-efficient hardware mechanism to dynamically detect the imbalances in different directions in each router and adaptively reallocate resources in the bottleneck router. The proposed mechanism is transparent to compiler and instruction placement algorithms. Besides, it can be easily applied as a supplementary hardware optimization to any instruction placement algorithm causing such kind of partial congestion problem. We evaluated the proposed hardware mechanism on a dataflow model, and the results show that our mechanism increases the average computational performance by 15.9%, with an increase in the average utilization of functional units by 15.6%. Crucially, our approach results in relatively small increase in the area and power consumption of less than 1%. In conclusion, the evaluation results suggest that our approach is an effective improvement for the efficiency of data transfer in dataflow processors.