Design of Neuron Net Function using Modified Radix-4 Booth Multiplier with a Flipped Logic Parallel Prefix Adder

摘要

This paper presents a full custom implementation of net function as a building block of neuron in an Artificial Neural Network system. The net function is implemented using radix-4 booth multiplier architecture. The main challenge or bottle neck in a booth multiplier architecture is designing an efficient adder. In this work, we propose a flipped logic parallel prefix adder to optimize the performance of the multiplier. By using this adder, the processing stages are able to be reduced more than a half, which resulting in a significant improvement of the propagation delay. The system has a total layout area of 0.027 mm^{2 with maximum operating frequency of 3.4 MHz. The circuit and layout design are implemented on 130nm CMOS technology.}