Wafer fabrication is the most complex process in Semiconductor Manufacturing Industry which includes the reentrant events, process queue time limitation and batch run dispatching.. The paper demonstrates a feasible dispatching algorithm -shortest inter cycle time- to balance WIP and shorten lots’ cycle time among production areas dynamically. It, embedded in our real-time dispatching mechanisms, is proved to reduce 32.5% waiting time compared to as-is method in real practice (not resulting from simulation models).
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