Area-Delay Product Efficient Design for Convolutional Neural Network Circuits Using Logarithmic Number Systems

摘要

In this paper, we have proposed area-delay product (ADP) efficient design for convolutional neural network (CNN) circuits using logarithmic number systems (LNS). By employing LNS-based schemes, the area overhead for large amount of conventional multipliers required in CNN circuits can be tremendously reduced. Simulation results show that our proposed design can achieve lower-error with almost 60% ADP savings compared with the conventional multipliers-based design, which is suitable for deep learning applications.