Channel Length Sizing for Power Minimization in Leakage-Dominated Digital Circuits

摘要

This paper presents an analytical power and timing model for leakage-dominated digital circuits. Using the model, we show that channel length upsizing can minimize total power consumption under timing and voltage constraints, and we present an analytical approach for finding the optimum channel length for power minimization of any digital circuit. We verify our model using a subthreshold 32-bit adder in a 65nm process, achieving a total power reduction of 47% at the optimum channel length, relative to minimum length sizing.