Perfect Column-Layered Two-Bit Message-Passing LDPC Decoder and Architectures

摘要

Flash and other memories may adopt multi-stage low-density parity-check (LDPC) decoders to reduce the average decoding latency and power consumption. To meet the increasingly tighter latency constraints of next-generation data centers, the earlier-stage decoders need to have better error-correcting capability and lower latency. To achieve this goal, this paper first develops a column-layered scheduling scheme for the 2-bit message-passing (TBMP) LDPC decoding algorithm, which has significant coding gain over the 3-bit Min-sum algorithm. The proposed column-layered scheme is perfect in the sense that it does not cause any coding gain degradation. Also by utilizing the 2-bit property, efficient VLSI architectures are designed for the column-layered and non-layered TBMP algorithms. Complexity analysis shows that, the layered (non-layered) TBMP decoder has more than 10 (8) times shorter latency at the cost of 53% (8%) larger area compared to a row-layered 3-bit Min-sum decoder for an example (17664, 16560) LDPC code.