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Hardware Implementation of Background Calibration Technique for TIADCs with Signals in Any Nyquist Bands

机译:具有任何奈奎斯特频段信号的TIADC背景校准技术的硬件实现

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We investigate a novel fully digital background calibration technique to mitigate the gain and timing mismatches in Time-Interleaved Analog-to-Digital Converters (TIADCs) for the wideband bandlimited input signal at any Nyquist zones. The correction scheme is simple by subtracting the image signals from the distorted signal. The channel mismatch parameters are estimated based on out-of-band error estimation. Neither an additional reference channel and nor a pilot input are required in calibration. A four-channel 60dB SÒR TIADC operating at 2.7GHz is used in both simulation and experimental implementation to validate the proposed calibration technique. The SNDR improvement is 16dB for a multi-tone input occupied at the third Nyquist band. The calibration method is validated on Altera FPGA DE4 board. In a Hardware-In-the-Loop emulation framework, the synthesized circuit works effectively and utilizes a very little amount of the hardware resource in the FPGA chip.
机译:我们研究了一种新颖的全数字背景校准技术,以减轻任何奈奎斯特区域的宽带受限输入信号在时间交错式模数转换器(TIADC)中的增益和时序失配。通过从失真信号中减去图像信号,校正方案很简单。基于带外误差估计来估计信道失配参数。校准不需要额外的参考通道和先导输入。在仿真和实验实现中均使用了一个工作于2.7GHz的四通道60dBSÒRTIADC,以验证所提出的校准技术。对于在第三奈奎斯特频带上占用的多音输入,SNDR的改善为16dB。校准方法已在Altera FPGA DE4板上验证。在硬件在环仿真框架中,合成电路有效地工作,并利用了FPGA芯片中很少的硬件资源。

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