A Scalable Fully Synthesized Phase-to-Digital Converter for Phase and Duty-Cycle Measurement of High-Speed Clocks

摘要

This work presents a Phase-to-Digital Converter (PDC) synthesisable from a standard cell library that enables the measurement of phase and duty-cycle of high-speed clocks. The resolution and sample rate of the PDC can be adjusted by the choice of the frequency of an additional input clock. This allows the use of the PDC in closed-loop systems for phase or duty-cycle adjustments and provides a way to minimize the power consumption of the circuit. Also a calculation method is proposed to model the PDC's behavior with respect to jitter. The design is tested on an FPGA with up to 650 MHz and implementation results at 2.5 GHz in a 65 nm CMOS process show the potential use of the PDC for phase alignment and duty-cycle adjustment in multi-gigabit transceivers with low hardware cost and low power.