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A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems

机译:用于2-PAM系统的具有40个并行度的40Gb / s全数字自适应降噪前馈滤波器和自适应决策反馈均衡器

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A 40Gb/s all-digital adaptive noise-suppression feed-forward filter/equalizer (AFFE) and adaptive decision feedback equalizer (ADFE) for 2-level pulse amplitude modulation (2-PAM) systems is presented. Batch mode coefficients update (BMCU) unit together with coefficients-lookahead scheme are proposed to achieve high parallelism architecture for ADFE. With these schemes, new extended incremental coefficients-lookahead filter architecture is proposed to provide high throughput rate and to reduce hardware complexity of parallel ADFE. Besides, feed-forward noise-suppression architecture is proposed for AFFE to provide better signal-to-noise ratio (SNR). The equalizer operates at 1 GHz system clock with 40 parallelisms is implemented in 40nm CMOS technology with a core area 0.23mm2. The measurement results verify the equalizer performance and the maximum throughput of 40Gb/s is achieved under 0.9V supply with 4.35pJ/bit energy efficiency.
机译:提出了一种用于2级脉冲幅度调制(2-PAM)系统的40Gb / s全数字自适应噪声抑制前馈滤波器/均衡器(AFFE)和自适应判决反馈均衡器(ADFE)。提出了批处理模式系数更新(BMCU)单元以及系数超前方案,以实现ADFE的高并行性体系结构。利用这些方案,提出了新的扩展增量系数超前滤波器架构,以提供高吞吐速率并降低并行ADFE的硬件复杂度。此外,为AFFE提出了前馈噪声抑制架构,以提供更好的信噪比(SNR)。均衡器以1 GHz系统时钟运行,具有40个并行度,采用40nm CMOS技术实现,核心面积为0.23mm 2 。测量结果验证了均衡器性能,在0.9V电源下以4.35pJ / bit的能效实现了40Gb / s的最大吞吐量。

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