A 56 Gb/s 6 mW 300 um2inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS

摘要

A 56 Gb/s inverter-based continuous time linear equalizer (CTLE) in 16 nm FinFET CMOS is presented. The inverters are biased with a regulated ground supply, using a ring oscillator based feedback loop that stabilizes the inverters' unity gain frequency fu and thus tracks PVT variations. The CTLE core measures only 20 um × 15 um and consumes 6 mW. Using the CTLE as the only means of RX equalization, the transceiver achieves 31% UI margin at BER of 1e-12 for a channel with 8 dB loss at 28 GHz.