A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS

摘要

Phase noise performance of ring-oscillator-based (RO-based) clock multipliers is typically limited by oscillator noise. The most power-efficient method for improving the phase noise of such clock multipliers is by increasing the oscillator noise suppression bandwidth (F_BW). While F_BW depends on the type of clock multiplier, the maximum achievable F_BW is limited by the reference frequency (F_ref). For instance, in phase-locked loops (PLLs) F_BW = F_ref/10, while multiplying delay-locked loops (MDLLs) [1] and injection-locked clock multipliers (ILCMs) [2] can achieve F_BW of F_ref/4 and F_ref/6, respectively. Exploiting this behavior, the MDLL in [1] and the ILCM in [2] achieved excellent performance at the expense of using a high-frequency low-noise reference (REF) clock and a small multiplication factor (N <; 10). One promising way to reduce F_ref in MDLLs/ILCMs involves increasing the injection rate by using both the positive and negative edges of the REF clock [3, 4] but at the cost of making jitter/spurious performance susceptible to duty cycle errors in the REF clock. While [3] demonstrated an effective means to correct such errors, it still needed a relatively high F_ref of 125MHz. In view of this, we present a method to quadruple the frequency of a conventional 54MHz Pierce XO and demonstrate its application using an RO-based ILCM achieving less than 370fs_rms integrated jitter at a 5GHz output. The proposed quadrupler acts as a low noise XO frequency multiplier and can be used to increase the bandwidth of MDLLs and ring/LC-based integer-or fractional-N PLLs also.