Advanced Metallizatisn Processes Integration as Manufacturing Worthy Solutions for > 10:1 Aspect Ratio Mid-Process TSV

摘要

For many years, TSV has become a key technology driver for 3D integration of heterogeneous devices. Among the different ways to create TSV, mid-process integration places the TSV realization between the front end and back end of line^[1][2]. The expansion of TSV based 3D integration market is in its critical phase today. On one hand, the need for 3D integration is clearly defined for some applications while on the other hand, the high cost of TSV integration coupled to the criticism in managing the mechanical warping of the wafers generated by the increasing surface of interposers as well as the use of highly stressed substrates like thick SOI appears as limiting its generalization. Among the solutions to overcome the wafer deformation, increasing the silicon thickness looks one of the most polyvalent one. However, in order to keep the same connections density, this will lead to an increase in the aspect ratio of the TSV which is generally fixed at 10:1 for metallization limitations reason and especially the PVD processes lack of step coverage^[3].