Blockage-aware terminal propagation for placement wirelength minimization

摘要

Wirelength is the most fundamental objective in placement because it also affects various placement metrics (routability, timing, etc.). Half-perimeter wirelength (HPWL) is a pervasive metric for circuit placement. However, preplaced blocks (i.e., blockages) might misguide an HPWL-based placer to generate a placement solution that incurs significant routing detours. Consequently, it is desirable to develop an effective method to resolve the HPWL-rooted routing detour problem for placement optimization. This paper presents an efficient, generic, yet effective terminal propagation algorithm as a pre-placement process which can readily be integrated into a traditional placement flow to improve wirelength (and routability). Our algorithm identifies a region for each preplaced terminal according to its connectivity, and applies a minimum-cost maximum flow algorithm to propagate all preplaced terminals to their feasible propagation locations with the minimum total propagation length. Experimental results show that our flow with terminal propagation can reduce both global routed wirelength and routing congestion by 4% on average, compared with one without terminal propagation. In particular, our work also provides a long unnoticed insight into placement optimization with blockages, which can be addressed with an efficient, generic, yet effective scheme.