A Simulation Study on a Cascade-pipeline BSI-Multi-Collection-Gate Image Sensor

摘要

This paper proposes a novel design of an ultra-high-speed image sensor. A light guide pipe or a convex pyramid charge collector is utilized to guide electrons from the backside photoelectron conversion layer to the frontside. The pixel configuration at the front side is divided into 4 concentric areas (guidance, collection, in-situ storage, and readout) with the cascade pipeline structure. Multi-furcation of each collection gate increases the frame count and lowers the readout rate from the outmost readout circuits. The simulation results show that the sensor can achieve the frame rate at 1 Gfps with 5.8% of crosstalk. Signals are then transferred to a stacked memory chip for continuous recording.