Overcoming interconnect scaling challenges using novel process and design solutions to improve both high-speed and low-power computing modes

摘要

Interconnect scaling in future CMOS technology nodes is projected to cause an unprecedented increase in resistance, making interconnects the key performance limiter instead of transistors. Both high-speed and low-power computing modes based on dynamically changing VDD and frequency will be the most impacted by this trend. To overcome this dilemma we present device-circuit-architecture solutions based on the reconfiguration of i) buffered interconnects and ii) execution architecture. Interconnect is dynamically reconfigured by either CMOS transistors or novel Insulator-Metal-Transition “via” devices. Processor execution resources are dynamically re-provisioned based on operating mode and activity metrics. With projected interconnect resistance, a simulated processor design shows 18% and 15% performance improvement from interconnect and execution architecture reconfiguration, respectively. When combined, these techniques provide 35% performance improvement in high-speed mode and energy efficiency in low-power mode.