首页> 外文会议>International Siberian Conference on Control and Communications >The new architectures of the class AB differential stages for the high-speed CMOS-BiJFET of the operational and differential difference amplifiers of the sensor analog interfaces
【24h】

The new architectures of the class AB differential stages for the high-speed CMOS-BiJFET of the operational and differential difference amplifiers of the sensor analog interfaces

机译:传感器模拟接口的运算和差分差分放大器的高速CMOS-BiJFET的AB类差分级的新架构

获取原文

摘要

The article considers the designed double-ended in the inputs and the current outputs class AB multichannel differential stages (MDS), intended to the work in the operational (op-amp) and differential difference (DDA) amplifiers, including at the low temperatures and the radiation exposure. The features of the considered MDSs is absence of the classical reference current sources, setting the steady-state behavior of the input transistors, and also the wide range of the active operation. The last quality is one of the conditions of the significant increase of the maximum slew rate of the op-amp and DDA (SRout). The suggested MDSs also don't impose the restrictions on the SRout, caused by the so-called “dynamic asymmetry” of their input stages (IS), which is connected with the inertance of the emitter (source) voltage followers, present in the structure of the IS of the high-speed op-amps. There are no followers in the considered MDS. This enables to obtain the maximum high-speed response of the op-amp (DDA) in the large signal operation, corresponding to their small signal operation conditions. The authors give the examples of construction of the studied DDA and op-amp based on the JFET-CMOS MDS. They present the simulation results of the op-amp with MDS for the XFab technological process, which show, that in the micro regime of the MDS (6÷100μA) the maximum slew rate lies in the range of 260-700 V/μs. The suggested architectures of the MDS enlarge the view of the design engineers about the new methods of construction of the input stages of the analog IP-modules for the systems-on-a-chip and add significantly to the classical circuitry of the op-amp and the DDA, realized on the base of modern technologies.
机译:本文考虑了输入端和电流输出端AB类多通道差分级(MDS)的设计双端,旨在用于运算放大器(op-amp)和差分差分(DDA)的工作,包括在低温和低温情况下的工作。辐射暴露。所考虑的MDS的特点是没有经典的参考电流源,它设置了输入晶体管的稳态行为,并且有效工作的范围也很广。最后的质量是大幅提高运算放大器和DDA(SRout)的最大压摆率的条件之一。建议的MDS也不会对SRout施加限制,这是由于其输入级(IS)的所谓“动态不对称性”引起的,该动态级与存在于发射极(源)电压跟随器的惯性有关。高速运算放大器的IS的结构。考虑的MDS中没有关注者。这样就可以在大信号操作中获得运算放大器(DDA)的最大高速响应,这与它们的小信号操作条件相对应。作者给出了基于JFET-CMOS MDS的DDA和运算放大器的构造示例。他们介绍了具有XDS工艺流程的MDS的运算放大器的仿真结果,结果表明,在MDS的微状态(6÷100μA)中,最大压摆率在260-700 V /μs的范围内。 MDS的建议体系结构扩大了设计工程师对片上系统模拟IP模块输入级构建新方法的看法,并极大地增加了运算放大器的经典电路和DDA,都是在现代技术的基础上实现的。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号