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Innovative laser enabled dual damascene process for ultra-fine line multi-layer routing for advanced packaging

机译:创新的激光技术实现了双镶嵌工艺,可进行超细线多层布线,以实现高级包装

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Fan out wafer level packaging (FOWLP) continues to be the main driver for advanced packaging. The major application nowadays is the single chip packaging with low routing. The continuous trend towards miniaturization, increasing performance and mobility of electronic devices drives interconnect density and integration, not only at the chip level, but also at interposer and package level. However, there is a continuing need for low cost packaging. While traditional organic flip-chip substrates using semi-additive processes (SAP) have not been able to scale to ultra-fine RDL pitches and via opening below 10um, photo-sensitive spin-on dielectrics and RDL processes used for wafer level packaging do not sufficiently address the cost reduction need. This paper presents the latest results from cost effective and innovative package RDL and micro via processes using excimer laser ablation, to meet the market's most stringent requirements. To enable panel and wafer based interposers to reduce RDL cost and scale interconnect pitch to 40um and below, excimer laser ablation is introduced as a direct patterning process that uses proven industrialized excimer laser sources to emit high-energy pulses at short wavelengths to remove polymer materials with high precision and high throughput. The combination of a high-power excimer laser source, large-field laser mask and precision projection optics enables the accurate replication and placement of fine resolution circuit patterns without the need for any wet-processing. In addition, with excimer laser patterning technology the industry gains a much wider choice of dielectric materials (photo and non-photo) to help achieve further reductions in manufacturing costs as well as enhancements in interposer and package performance. In this paper, we propose new pattering process that uses excimer laser ablation to integrate via and RDL traces in one patterning process step, followed by seed layer deposition, plating and planarization steps. A new integration process flow is proposed, and its technical robustness and commercial advantages have been demonstrated. The capability of this excimer laser patterning process in non-photo materials will be discussed. We will present electrical and reliability data of Via and RDL traces patterned by Excimer laser in non photo material. The commercial benefits of the new laser based patterning process as compared to the current process of record (POR) will be highlighted.
机译:扇出晶圆级封装(FOWLP)仍然是高级封装的主要驱动力。如今的主要应用是低布线的单芯片封装。小型化,电子设备性能和移动性不断发展的持续趋势不仅在芯片级,而且在中介层和封装级都驱动着互连密度和集成度。然而,对低成本包装的持续需求。尽管使用半加成工艺(SAP)的传统有机倒装芯片基板无法缩放至超细RDL间距并无法通过10um以下的开口进行开口,但用于晶圆级封装的光敏旋涂电介质和RDL工艺却无法实现充分满足降低成本的需求。本文介绍了采用准分子激光烧蚀的经济高效且创新的封装RDL和微通孔工艺的最新结果,可满足市场最严格的要求。为了使基于面板和晶圆的中介层能够降低RDL成本并将互连间距缩小至40um及以下,引入了准分子激光烧蚀作为一种直接构图工艺,该工艺使用成熟的工业化准分子激光源在短波长下发射高能脉冲以去除聚合物材料高精度和高吞吐量。高功率准分子激光源,大视野激光掩模和精密投影光学器件的结合,可以精确复制和放置精细分辨率的电路图案,而无需进行任何湿法处理。此外,借助准分子激光图案化技术,该行业获得了更多的电介质材料选择(光敏和非光敏),以帮助进一步降低制造成本以及增强内插器和封装的性能。在本文中,我们提出了一种新的构图工艺,该工艺采用准分子激光烧蚀在一个构图工艺步骤中集成通孔和RDL迹线,然后进行种子层沉积,电镀和平面化步骤。提出了一种新的集成工艺流程,并证明了其技术鲁棒性和商业优势。将讨论在非照相材料中这种准分子激光图案化工艺的能力。我们将介绍由准分子激光在非感光材料中构图的Via和RDL迹线的电气和可靠性数据。与当前的记录过程(POR)相比,新的基于激光的图案化过程的商业优势将得到重点介绍。

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