Active reliability monitor: Defect level extrinsic reliability monitoring on 22nm POWER8 and zSeries processors

摘要

Monitoring extrinsic reliability performance in a given technology is often performed in a passive manner. Semiconductor devices (die) are sampled out of production environment, subjected to a series of electrical and mechanical stresses, and finally tested extensively to determine if stressing produced additional fails. This strategy is prone to missing issues which are localized to a lots or wafers and is not likely to identify potential field reliability problems early enough to remove samples prior to shipment to the customer. We have created a system which continuously scans memory array repairs (correctable errors) across multiple test steps including Burn In and Voltage Screen, applies a pattern classification algorithm, and enables reliability information to be collected for every die. We will show that monitoring extrinsic defects at Wafer Final Test and through Burn In on every die for every product in a technology is crucial to a robust technology reliability strategy. Additionally we demonstrate a low cost high efficiency system, the Active Reliability Monitor, which accomplishes that goal using 22nm POWER8 and zSeries processor data. The system is shown to provide similar quality data to traditional reliability screening methods while also allowing for automated real time reaction to reliability indicators, specific-defect-type monitoring, and robust monitoring across products in the technology. The tool has enabled the identification of new screen procedures used for the containment of several problematic lots and rapid evaluation of the reliability degradation for any suspect reliability vintages.