Subthreshold Passive RFID Tag's Baseband Processor Core Design with Custom Modules and Cells

摘要

Subthreshold ultra-low-power passive RFID tag's baseband processor core design with custom logic cells is presented in this paper, based on EPC C1G2 protocol. To deal with the critical timing and wide-range-PVT variation problems of the processor at very low power supply, and for the consideration of limited availability of RF power, power-aware scheme is applied to the key modules, including PIE decoding and command receiving. And Galoi linear feedback shift register (LFSR) and double-edge-triggered techniques help to improve clock efficiency and reduce the impact of frequency variation in data link portions. Additionally, a novel custom ratioed logic style is adopted in key modules to fundamentally solve the speed problem at ultra-low-voltage. The proposed baseband processor was fabricated in 90nm CMOS as well as the regular design with the same function. In measurement the proposed design indicates good robustness and much more competent for subthreshold operation. It can operate below 0.3 V with power consumption below 130 nW.