Closed loop structure to prevent couplings on CMOS process

摘要

This paper represents a layout solution to reduce the on-chip couplings in between two BALUNs, which is implemented by UMC 28iim CMOS process. In advanced CMOS technology and circuit application applied for higher frequency, couplings are always an issue to be solved, which are mostly coming through substrate, magnetic fields or electric fields. A floating ring is in use to block the magnetic couplings from other devices for around 3dB, which are the hardest parts to be eliminated. 3D EM simulations are also presented as measured results well. Moreover, different structures of floating metal ring are also discussed and compared by EM simulation in this paper.