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A spur-reduction Delta-Sigma Modulator with efficient dithering for fractional frequency synthesizer

机译:用于分数频率合成器的具有有效抖动的杂散抑制Delta-Sigma调制器

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A spur-reduction dither structure is presented to achieve low fractional spurs for a wideband frequency synthesizer. The dither structure is added to the digital multi-stage noise shaping (MASH) Delta-Sigma Modulator (DSM) for the wideband fractional-N frequency synthesizer. Traditionally, the MASH can generate spur tone in fractional frequency synthesizers. We propose to add a simple 8-bit linear feedback shift register (LFSR) to reduce spur tone. The MASH Structure is dithered using FPGA to reduce the spur. It improves in-band fractional spur about 13dBc/Hz at 50 kHz offset and achieves high frequency resolution of 0.001Hz.
机译:提出了一种减少杂散的抖动结构,以实现宽带频率合成器的低杂散。抖动结构被添加到用于宽带分数N频率合成器的数字多级噪声整形(MASH)Delta-Sigma调制器(DSM)中。传统上,MASH可以在分数频率合成器中产生杂音。我们建议添加一个简单的8位线性反馈移位寄存器(LFSR)以减少杂散音。使用FPGA抖动MASH结构以减少杂散。它在50 kHz偏移时将带内分数杂散提高了约13dBc / Hz,并实现了0.001Hz的高频分辨率。

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