Design and synthesis of goldschmidt algorithm based floating point divider on FPGA

摘要

This paper presents a single precision floating point division based on Goldschmidt computational division algorithm. The Goldschmidt computational algorithm is implemented using 32-bit floating point multiplier and subtractor. The salient feature of this proposed design is that the module for computing mantissa in 32-bit floating point multiplier is designed using a 24-bit Vedic multiplication (Urdhva-triyakbhyam-sutra) technique. 32-bit floating point multiplier, designed using Vedic multiplication technique, yields a higher computational speed and is used to increase the performance of the floating point divider. The main objective is to synthesize the proposed floating point divider on FPGA using Verilog hardware description language (HDL). The proposed floating point divider can be used in the design of floating point divide - add fused (DAF) architecture.