Self-error detecting and correcting hybrid DAC on 45nm technology

摘要

This paper contains self error detecting and correcting technique for high speed and performance applications. DAC (digital to analog converter) is the basic building block for communication purpose. Self detecting and correcting technique is connected at the output of Digital to analog converter. For achieving high speed resolution hybrid architecture of DAC is used. In which LSB are implemented using binary weighted architecture and MSB are implemented using unary architecture The design of the circuit is done in Cadence Virtuoso with CMOS 45 nm technology.