A fast reliability screening technique for identification of trap generation

摘要

Trap generation under BTI/TDDB stress for extremely scaled NMOSFETs and PMOSFETs is investigated. Trap identification and localization using SILC Spectrum technique is demonstrated. It has been verified that BTI/TDDB stress leads to trap generation primarily at IL/HK intermix for PMOSFETs, and primarily at HK layer in case of NMOSFETs. The advantage of this technique is it requires minimal post measurement analysis and hence is ideal for quick screening of trap generation. Atomistic simulations close to operation regime and stress regime are performed on both NMOSFETs and PMOSFETs. Atomistic simulations indicate that the formation energy for hole traps in IL/HK intermix layer is the lowest in PMOSFETs whereas formation energy is the lowest for electron traps in HK layer for NMOSFETs. The results as verified by performing atomistic further validate the findings from SILC Spectrum technique.