An Analysis of Parallel Prefix Adders Regarding the Design of Low-Power Data Oriented Adders

摘要

The paper presents results of detailed analysis of power dissipated by parallel prefix adders when operating on specific data. Using extended model of CMOS gate power consumption deepened analysis can be done. The model take into consideration changes of input vectors, not only switching activity of signals. In the research several structures of adders have been analyzed with various scenarios of input data. Results show that for different kind of summed data different structures of adders are better considering reduction of power consumption.