Single-stage offset-cancelled latched comparator scheduled by multi-level control on reset switch

摘要

A single-stage hardware is scheduled for multiple operations, reset, offset cancellation, pre-amplification and latch. Applying multi-level voltage on gate terminal of the reset switch controls the strength of positive feedback devices and manages multiple operations. Also, with reliable control on positive feedback, a high-gain offset cancellation loop can be formed with no longer need to auxiliary amplifier. A new read-out circuit is also proposed to reduce the load capacitance of the next stage and enhance the comparison speed. Worst-Case simulation results confirms that the proposed comparator can detect 2mVolts input difference, at all process corners, in presence of 50mVolts input offset voltage, at 800MS/s comparison rate. The Monte-Carlo analysis for 100 iterations on input offset shows that the input referred offset would be improved to 640μV while was 17mVolts at 1σ before correction. Power consumption is 0.45mW at 800MS/s comparison speed. Simulations are performed for all corner conditions using the BSIM3v3 model of a 0.18μm CMOS technology.