A low-complexity fast-locking digital PLL with multi-output bang-bang phase detector

摘要

This paper presents a locking-accelerated DPLL based on multi-output bang-bang phase detector (MOBBPD) with reused most significant bits (MSBs). The bang-bang structure has simple implementation by eliminating the sensitive time-to-digital converter (TDC), while MOBBPD allows for reduced loop locking-time due to the multi-output. To further accelerate the loop locking, a scheme of reusing the MSBs is proposed to signify the large phase-difference at the early stage of lock acquisition, hence reducing the phase difference quickly. The low complexity of the design is maintained due to the simple structure. The proposed DPLL is designed using a 0.18-μm CMOS process. It generates an output clock frequency range of 1-2.2 GHz with 7.8-17.2 MHz input reference frequency. The power consumption is 5.1 mW while the locking speed is improved by around 20 times improvement compared to without reusing the MSBs.