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Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing

机译:28nm FD-SOI技术在低至100MK中的Quantum Computing中的28nm FD-SOI技术的可变性评估

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Variability of28nm FD-SOI transistors is evaluated for the first time down to ultra low temperatures (UL T), at T= 1 00mK. High performance is achieved at UL T for short channel transistors, with $mathrm{I}_{mathrm{ON}} > 1mathrm{mA}mu mathrm{m}$ and $mathrm{I}_{mathrm{OFF}}$ below the equipment accuracy <1 fA, in particular by keeping advantage of forward back biasing (FBB), with the same efficiency from room temperature (R T) down to 100mK. The physical origins of MOSFET mismatch at ULT are studied, highlighting the impact of the charge fluctuations increase on both threshold voltage $(mathrm{V}_{mathrm{TH}})$ and current gain factor $(eta)$ variabilities. Besides that, we demonstrated that the increase of $mathrm{V}_{mathrm{TH}}$ and $eta$ variabilities at low temperature remains reasonably low in comparison to RT values and other CMOS technologies, so that it should not be detrimental to circuit operation in this range of temperatures.
机译:变异of28nm FD-SOI晶体管的首次评价下降到超低温度(UL T),在T = 1个00mK。高性能在ULŤ实现了短沟道晶体管,与 $ mathrm {I} _ { mathrm {ON}}> 1 mathrm {毫安} 亩 mathrm {M} $ $ mathrm {i} _ { mathrm {关闭}} $ 下面的设备精度<1为fA,特别是通过从室温保持前进后退偏置的优点(FBB),具有相同的效率(R T)下降到100mK。在ULT MOSFET失配的物理起源进行了研究,突出的电荷波动的影响增加在两个阈值电压 $( mathrm {V} _ { mathrm {TH}})$ 与当前增益系数 $(测试版)$ < /特克斯> 可变性。此外,我们证明了增加 $ mathrm {V} _ { mathrm {TH}} $ $ beta $ 变率在低温下保持在比较RT值和其他CMOS技术合理地低,所以,它不应该在该温度范围内是有害的电路的操作。

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