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VLSI design methods for low power embedded encryption

机译:VLSI用于低功耗嵌入式加密的设计方法

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Intelligent things, medical devices, vehicles and factories, all part of cyberphysical systems, will only be secure if we can build devices that can perform the mathematically demanding cryptographic operations in an efficient way. Unfortunately, many of devices operate under extremely limited power, energy and area constraints. Yet we expect that they can execute, often in real-time, the symmetric key, public key and/or hash functions needed for the application. At the same time, we request that the implementations are also secure against a wide range of physical attacks. This presentation will focus on the design methods to realize cryptographic operations on resource constrained devices. To reach the extremely low power, low energy and area budgets, we need to consider in an integrated way the protocols, the algorithms, the architectures and the circuit aspects of the application. These concepts will be illustrated with the design of several cryptographic co-processors suitable for implementation in embedded context.
机译:智能事物,医疗器械,车辆和工厂,包括网络耳机系统的所有部分,如果我们可以以有效的方式构建可以以有效的方式执行数学上要求苛刻的加密操作的设备。不幸的是,许多设备在极其有限的功率,能量和区域约束下运行。然而,我们预计他们可以实时地执行应用程序所需的对称密钥,公钥和/或哈希函数。与此同时,我们要求实现对广泛的物理攻击也可以安全。此演示文稿将侧重于在资源受限设备上实现加密操作的设计方法。为了达到极低的功率,低能量和区域预算,我们需要以综合方式考虑协议,算法,架构和应用程序的电路方面。这些概念将通过设计在嵌入的上下文中的实施方式设计了几个加密协处理器。

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