Heterogeneous Hardware Accelerators with Hybrid Interconnect: An Automated Design Approach

摘要

Although heterogeneous multicore systems are widely used in both academia and industry, system performance of such systems does not scale when increasing the number of processing cores. The main reason is due to the communication overhead which increases greatly with the increasing number of cores. In this paper, we propose an automated design approach to build a heterogeneous hardware accelerator system, one of the main trends in heterogeneous multicore, with hybrid interconnect. Our approach takes communication patterns of an application into account so that data communication of computing cores is optimized while keeping hardware resources usage for the whole system minimal. Experimental results in both an embedded and a high-performance computing platforms show that the design approach improves system performance by up to 1.83× for the embedded platform and by up to 1.53× for the high-performance computing platform. Energy consumption of the embedded platform is reduced by up to 50.3% while energy consumption of kernels in the high-performance platform is reduced by up 54.2%, compared to baseline systems.