Bus Centric Synchronous Message Exchange for Hardware Designs

摘要

In this work we present a new design and implementation of the Synchronous Message Exchange model. The new version uses explicit busses, which may include multiple fields, and where a components may use a bus for both reading and writing, whereas the original version allowed only reading from or writing to a bus, which triggered a need for some busses to exist in two versions for different directions. In addition to the new and improved bus-model, the new SME version also produces traces that may be used for validating a later VHDL implementation of the designed component, and can produce a graphical representation of a design to help with debugging.